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november 1991 order number: 271077-006 m82C288 bus controller for m80286 processors (m82C288-10, m82C288-8, m82C288-6) military y provides commands and controls for local and system bus y wide flexibility in system configurations y implemented in high speed chmos iii technology y fully compatible with the hmos m82288 y fully static device y single a 5v supply y available in 20 pin cerdip package (see packaging spec, order y 231369) the intel m82C288 bus controller is a 20-pin chmos iii component for use in m80c286 microsystems. the m82C288 is fully compatible with its predecessor the hmos m82288. the bus controller is fully static and supports a low power mode. the bus controller provides command and control outputs with flexible timing options. separate command outputs are used for memory and i/o devices. the data bus is controlled with separate data enable and direction control signals. two modes of operation are possible via a strapping option: multibus compatible bus cycles, and high speed bus cycles. 271077 1 figure 1. m82C288 block diagram 20 pin cerdip package 271077 2 figure 2. m82C288 pin configuration
m82C288 table 1. pin description the following pin function descriptions are for the m82C288 bus controller. symbol type name and function clk i system clock provides the basic timing control for the m82C288 in an m80286 microsystem. its frequency is twice the internal processor clock frequency. the falling edge of this input signal establishes when inputs are sampled and command and control outputs change. s0 ,s1 i bus cycle status starts a bus cycle and, along with m/io , defines the type of bus cycle. these inputs are active low. a bus cycle is started when either s1 or s0 is sampled low at the falling edge of clk. setup and hold times must be met for proper operation. m80286 bus cycle status definition m/io s1 s0 type of bus cycle 0 0 0 interrupt acknowledge 0 0 1 i/o read 0 1 0 i/o write 0 1 1 none; idle 1 0 0 halt or shutdown 1 0 1 memory read 1 1 0 memory write 1 1 1 none; idle m/io i memory or i/o select determines whether the current bus cycle is in the memory space or i/o space. when low, the current bus cycle is in the i/o space. setup and hold times must be met for proper operation. mb i multibus mode select determines timing of the command and control outputs. when high, the bus controller operates with multibus i compatible timings. when low, the bus controller optimizes the command and control output timing for short bus cycles. the function of the cen/aen input pin is selected by this signal. this input is typically a strapping option and not dynamically changed. cenl i command enable latched is a bus controller select signal which enables the bus controller to resopnd to the current bus cycle being initiated. cenl is an active high input latched internally at the end of each t s cycle. cenl is used to select the appropriate bus controller for each bus cycle in a system where the cpu has more than one bus it can use. this input may be connected to v cc to select this m82C288 for all transfers. no control inputs affect cenl. setup and hold times must be met for proper operation. cmdly i command delay allows delaying the start of a command. cmdly is an active high input. if sampled high, the command output is not activated and cmdly is again sampled at the next clk cycle. when sampled low the selected command is enabled. if ready is detected low before the command output is activated, the m82C288 will terminate the bus cycle, even if no command was issued. setup and hold times must be satisified for proper operation. this input may be connected to gnd if no delays are required before starting a command. this input has no effect on m82C288 control outputs. ready i ready indicates the end of the current bus cycle. ready is an active low input. multibus i mode requires at least one wait state to allow the command outputs to become active. ready must be low during reset, to force the m82C288 into the idle state. setup and hold times must be met for proper operation. the m82c284 drives ready low during reset. 2
m82C288 table 1. pin description (continued) symbol type name and function cen/aen i command enable/address enable controls the command and den outputs of the bus controller. cen/aen inputs may be asynchronous to clk. setup and hold times are given to assure a guaranteed response to synchronous inputs. this input may be connected to v cc or gnd. when mb is high this pin has the aen function. aen is an active low input which indicates that the cpu has been granted use of a shared bus and the bus controller command outputs may exit 3-state off and become inactive (high). aen high indicates that the cpu does not have control of the shared bus and forces the command outputs into 3-state off and den inactive (low). when mb is low this pin has the cen function. cen is an unlatched active high input which allows the bus controller to activate its command and den outputs. with mb low, cen low forces the command and den outputs inactive but does not tristate them. ale o address latch enable controls the address latches used to hold an address stable during a bus cycle. this control output is active high. ale will not be issued for the halt bus cycle and is not affected by any of the control inputs. mce o master cascade enable signals that a cascade address from a master m8259a interrupt controller may be placed onto the cpu address bus for latching by the address latches under ale control. the cpu's address bus may then be used to broadcast the cascade address to slave interrupt controllers so only one of them will respond to the interrupt acknowledge cycle. this control output is active high. mce is only active during interrupt acknowledge cycles and is not affected by any control input. using mce to enable cascade address drivers requires latches which save the cascade address on the falling edge of ale. den o data enable controls when data transceivers connected to the local data bus should be enabled. den is an active high control output. den is delayed for write cycles in the multibus i mode. dt/r o data transmit/receive establishes the direction of data flow to or from the local data bus. when high, this control output indicates that a write bus cycle is being performed. a low indicates a read bus cycle. den is always inactive when dt/r changes states. this output is high when no bus cycle is active. dt/r is not affected by any of the control inputs. iowc o i/o write command instructs an i/o device to read the data on the data bus. this command output is active low. the mb and cmdly input control when this output becomes active. ready controls when it becomes inactive. iorc o i/o read command instructs an i/o device to place data onto the data bus. this command output is active low. the mb and cmdly input control when this output becomes active. ready controls when it become inactive. mwtc o memory write command instructs a memory device to read the data on the data bus. this command output is active low. the mb and cmdly inputs control when this output becomes active. ready controls when it becomes inactive. mrdc o memory read command instructs the memory device to place data onto the data bus. this command output is active low. the mb and cmdly inputs control when this output becomes active. ready controls when it becomes inactive. 3
m82C288 table 1. pin description (continued) symbol type name and function inta o interrupt acknowledge tells an interrupting device that its interrupt request is being acknowledged. this command output is active low. the mb and cmdly inputs control when this output becomes active. ready controls when it becomes inactive. v cc system power: a 5v power supply gnd system ground: 0v table 2. command and control outputs for each type of bus cycle type of m/io s1 s0 command dt/r ale, den mce bus cycle activated state issued? issued? interrupt acknowledge 0 0 0 inta low yes yes i/o read 0 0 1 iorc low yes no i/o write 0 1 0 iowc high yes no none; idle 0 1 1 none high no no halt/shutdown 1 0 0 none high no no memory read 1 0 1 mrdc low yes no memory write 1 1 0 mwtc high yes no none; idle 1 1 1 none high no no operating modes two types of buses are supported by the m82C288: multibus i and non-multibus i. when the mb input is strapped high, multibus i timing is used. in multibus i mode, the m82C288 delays com- mand and data activation to meet ieee-796 require- ments on address to command active and write data to command active setup timing. multibus i mode requires at least one wait state in the bus cycle since the command outputs are delayed. the non- multibus i mode does not delay any outputs and does not require wait states. the mb input affects the timing of the command and den outputs. command and control outputs the type of bus cycle performed by the local bus master is encoded in the m/io ,s1 and s0 inputs. different command and control outputs are activat- ed depending on the type of bus cycle. table 2 indi- cates the cycle decode done by the m82C288 and the effect on command, dt/r , ale, den and mce outputs. bus cycles come in three forms: read, write, and halt. read bus cycles include memory read, i/o read, and interrupt acknowledge. the timing of the associated read command outputs (mrdc , iorc , and inta ), control outputs (ale, den, dt/r ) and control inputs (cen/aen , cenl, cmdly, mb, and ready ) are identical for all read bus cycles. read cycles differ only in which command output is acti- vated. the mce control output is only asserted dur- ing interrupt acknowledge cycles. write bus cycles activate different control and com- mand outputs with different timing than read bus cy- cles. memory write and i/o write are write bus cy- cles whose timing for command outputs (mwtc and iowc ), control outputs (ale, den, dt/r ) and con- trol inputs (cen/aen , cenl, cmdly, mb and ready ) are identical. they differ only in which com- mand output is activated. halt bus cycles are different because no command or control output is activated. all control inputs are ignored until the next bus cycle is started via s1 and s0 . static operation all m82C288 circuitry is of static design. internal reg- isters and logic are static and require no refresh as with dynamic circuit design. this eliminates the mini- mum operating frequency restriction placed on the hmos m82288. the chmos iii m82C288 can oper- ate from dc to the appropriate upper frequency limit. 4
m82C288 the clock may be stopped in either state (high/ low) and held there indefinitely. power dissipation is directly related to operating fre- quency. as the system frequency is reduced, so is the operating power. when the clock is stopped to the m82C288, power dissipation is at a minimum. this is useful for low-power and portable applica- tions. functional description description the m82C288 bus controller is used in m80286 sys- tems to provide address latch control, data trans- ceiver control, and standard level-type command outputs. the command outputs are timed and have sufficient drive capabilities for large ttl buses and meet all ieee-796 requirements for multibus i. a special multibus i mode is provided to satisfy all address/data setup and hold time requirements. command timing may be tailored to special needs via a cmdly input to determine the start of a com- mand and ready to determine the end of a com- mand. connection to multiple buses are supported with a latched enable input (cenl). an address decoder can determine which, if any, bus controller should be enabled for the bus cycle. this input is latched to allow an address decoder to take full advantage of the pipelined timing on the m80286 local bus. buses shared by several bus controllers are sup- ported. an aen input prevents the bus controller from driving the shared bus command and data signals except when enabled by an external multi- bus i type bus arbiter. separate den and dt/r outputs control the data transceivers for all buses. bus contention is eliminat- ed by disabling den before changing dt/r . the den timing allows sufficient time for tristate bus driv- ers to enter 3-state off before enabling other driv- ers onto the same bus. the term cpu refers to any m80286 processor or m80286 support component which may become an m80286 local bus master and thereby drive the m82C288 status inputs. processor cycle definition any cpu which drives the local bus uses an internal clock which is one half the frequency of the system clock (clk) (see figure 3). knowledge of the phase of the local bus master internal clock is required for proper operation of the m80286 local bus. the local bus master informs the bus controller of its internal clock phase when it asserts the status signals. status signals are always asserted beginning in phase 1 of the local bus master's internal clock. m82c284 271077 3 (for reference) figure 3. clk relationship to the processor clock and bus t-states 5
m82C288 bus state definition the m82C288 bus controller has three bus states (see figure 4): idle (t i ) status (t s ) and command (t c ). each bus state is two clk cycles long. bus state phases correspond to the internal cpu proces- sor clock phases. the t i bus state occurs when no bus cycle is cur- rently active on the m80286 local bus. this state may be repeated indefinitely. when control of the local bus is being passed between masters, the bus remains in the t i state. 271077 4 figure 4. m82C288 bus states bus cycle definition the s1 and s0 inpus signal the start of a bus cycle. when either input becomes low, a bus cycle is started. the t s bus state is defined to be the two clk cycles during which either s1 or s0 are active (see figure 5). these inputs are sampled by the m82C288 at every falling edge of clk. when either s1 and s0 are sampled low, the next clk cycle is considered the second phase of the internal cpu clock cycle. the local bus enters the t c bus state after the t s state. the shortest bus cycle may have one t s state and one t c state. longer bus cycles are formed by repeating t c state. a repeated t c bus state is called a wait state. the ready input determines whether the current t c bus state is to be repeated. the ready input has the same timing and effect for all bus cycles. ready is sampled at the end of each t c bus state to see if it is active. if sampled high, the t c bus state is repeated. this is called inserting a wait state. the control and command outputs do not change during wait states. when ready is sampled low, the current bus cy- cle is terminated. note that the bus controller may enter the t s bus state directly from t c if the status lines are sampled active at the next falling edge of clk. 271077 5 figure 5. bus cycle definition 6
m82C288 figures 6 through 10 show the basic command and control output timing for read and write bus cycles. halt bus cycles are not shown since they activate no outputs. the basic idle-read-idle and idle-write-idle bus cycles are shown. the signal label cmd repre- sents the appropriate command output for the bus cycle. for figures 6 through 10, the cmdly input is connected to gnd and cenl to v cc . the effects of cenl and cmdly are described later in the section on control inputs. figures 6, 7, and 8 show non-multibus i cycles. mb is cnonected to gnd while cen is connected to v cc . figure 6 shows a read cycle with no wait states while figure 7 shows a write cycle with one wait state. the ready input is shown to illustrate how wait states are added. 271077 6 figure 6. idle-read-idle bus cycles with mb e 0 271077 7 figure 7. idle-write-idle bus cycles with mb e 0 7
m82C288 bus cycles can occur back to back with no t i bus states between t c and t s . back to back cycles do not affect the timing of the command and control outputs. command and control outputs always reach the states shown for the same clock edge (within t s ,t c or following bus state) of a bus cycle. a special case in control timing occurs for back to back write cycles with mb e 0. in this case, dt/r and den remain high between the bus cycles (see figure 8). the command and ale output timing does not change. figures 9 and 10 show a multibus i cycle with mb e 1. aen and cmdly are connected to gnd. the effects of cmdly and aen are described later in the section on control inputs. figure 9 shows a read cycle with one wait state and figure 10 shows a write cycle with two waits states. the second wait state of the write cycle is shown only for example purposes and is not required. the ready input is shown to illustate how wait states are added. 271077 8 figure 8. write-write bus cycles with mb e 0 271077 9 figure 9. idle-read-idle bus cycles with 1 wait state and with mb e 1 8
m82C288 271077 10 figure 10. idle-write-idle bus cycles with 2 wait states and with mb e 1 the mb control input affects the timing of the com- mand and den outputs. these outputs are automat- ically delayed in multibus i mode to satisfy three requirements: 1) 50 ns minimum setup time for valid address be- fore any command output becomes active. 2) 50 ns minimum setup time for valid write data be- fore any write command output becomes active. 3) 65 ns maximum time from when any read com- mand becomes inactive until the slave's read data drivers read 3-state off. three signal transitions are delayed by mb e 1as compared to mb e 0: 1) the high to low transition of the read com- mand outputs (iorc , mrdc , and inta ) are de- layed one clk cycle. 2) the high to low transition of the write com- mand outputs (iowc nd mwtc ) are delayed two clk cycles. 3) the low to high transition of den of write cy- cles is delayed one clk cycle. back to back bus cycles with mb e 1 do not change the timing of any of the command or control outputs. den always becomes inactive between bus cycles with mb e 1. except for a halt or shutdown bus cycle, ale will be issued during the second half of t s for any bus cy- cle. ale becomes inactive at the end of the t s to allow latching the address to keep it stable during the entire bus cycle. the address outputs may change during phase 2 of any t c bus state. ale is not affected by any control input. figure 11 shows how mce is timed during interrupt acknlwedged (inta) bus cycles. mce is one clk cycle longer than ale to hold the cascade address from a master m8259a valid after the falling edge of ale. with the exception of the mce control output, an inta bus cycle is identical in timing to a read bus cycle. mce is not affected by any control input. 9
m82C288 271077 11 figure 11. mce operation for an inta bus cycle control inputs the control inputs can alter the basic timing of com- mand outputs, allow interfacing to multiple buses, and share a bus between different masters. for many m80286 systems, each cpu will have more than one bus which may be used to perform a bus cycle. normally, a cpu will only have one bus con- troller active for each bus cycle. some buses may be shared by more than one cpu (i.e., multibus) re- quiring only one of them use the bus at a time. systems with multiple and shared buses use two control input signals of the m82C288 bus controller, cenl and aen (see figure 12). cenl enables the bus controller to control the current bus cycle. the aen input prevents a bus controller from driving its command outputs. aen high means that another bus controller may be driving the shared bus. in figure 12, two buses are shown: a local bus and a multibus i. only one bus is used for each cpu bus cycle. the cenl inputs of the bus controller select which bus controller is to perform the bus cy- cle. an address decoder determines which bus to use for each bus cycle. the m82C288 connected to the shared multibus i must be selected by cenl and be given access to the multibus i by aen before it will begin a multibus i operation. cenl must be sampled high at the end of the t s bus state (see waveforms) to enable the bus control- ler to activate its command and control outputs. if sampled low the commands and den will not go active and dt/r will remain high. the bus control- ler will ignore the cmdly, cen and ready inputs until another bus cycle is started via s1 and s0 . since an address decoder is commonly used to identify which bus is required for each bus cycle, cenl is latched to avoid the need for latching its inputs. the cenl input can affect the den control output. when mb e 0, den normally becomes active dur- ing phase 2 of t s in write bus cycles. this transition occurs before cenl is sampled. if cenl is sampled low, the den output will be forced low during t c as shown in the timing waveforms. when mb e 1, cen/aen becomes aen . aen con- trols when the bus controller command outputs en- ter and exit 3-state off. aen is intended to be driv- en by a multibus i type bus arbiter, which assures only one bus controller is driving the shared bus at any time. when aen makes a low to high tran- sition, the command outputs immediately enter 3-state off and den is forced inactive. an inactive den should force the local data transceivers con- nected to the shared data bus into 3-state off (see figure 12). the low to high transition of aen should only occur during t i or t s bus states. the high to low transition of aen signals that the bus controller may now drive the shared bus com- mand signals. since a bus cycle may be active or be in the process of starting, aen can become active during any t-state. aen low immediately allows den to go the appropriate state. three clk edges later, the command outputs will go active (see timing waveforms). the multibus i requires this delay for the address and data to be valid on the bus before the command becomes active. when mb e 0, cen/aen becomes cen. cen is an asynchronous input which immediately affects the command and den outputs. when cen makes a high to low transition, the commands and den 10
m82C288 are immediately forced inactive. when cen makes a low to high transition, the commands and den outputs immediately go to the appropriate state (see timing waveforms). ready must still become active to terminate a bus cycle if cen remains low for a selected bus controller (cenl was latched high). some memory or i/o systems may require more ad- dress or write data setup time to command active than provided by the basic command output timing. to provide flexible command timing, the cmdly in- put can delay the activation of command outputs. the cmdly input must be sampled low to activate the command outputs. cmdly does not affect the control outputs, ale, mce, den, and dt/r . 271077 12 figure 12. system use of aen and cenl 11
m82C288 cmdly is first sampled on the falling edge of the clk ending t s . if sampled high, the command out- put is not activated, and cmdly is again sampled on the next falling edge of clk. once sampled low, the proper command output becomes active immediately if mb e 0. if mb e 1, the proper com- mand goes active no earlier than shown in figures 9 and 10. ready can terminate a bus cycle before cmdly allows a command to be issued. in this case no commands are issued an the bus controller will de- activate den and dt/r in the same manner as if a command has been issued. waveforms discussion the waveforms show the timing relationships of in- puts and outputs and do not show all possible tran- sitions of all signals in all modes. instead, all signal timing relationships are shown via the general cas- es. special cases are shown when needed. the waveforms provide some functional descriptions of the m82C288; however, most functional descriptions are provided in figures 5 through 11. to find the timing specification for a signal transition in a particular mode, first look for a special case in the waveforms. if no special case applies, then use a timing specification for the same or related func- tion in another mode. 12
m82C288 absolute maximum ratings * case temperature under bias b 55 cto a 125 c storage temperature b 65 cto a 150 c voltage on any pin with respect to gnd b 0.5v to a 7v power dissipation 1 watt notice: this data sheet contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest data sheet be- fore finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol description min max unis t c case temperature (instant on) b 55 a 125 c v cc digital supply voltage 4.75 5.25 v d.c. characteristics (over specified operating conditions) symbol parameter min max units comments v il input low voltage b 0.5 0.8 v v ih input high voltage 2.0 v cc a 0.5 v v ilc clk input low voltage b 0.5 0.6 v v ihc clk input high voltage 3.8 v cc a 0.5 v v ol output low voltage command outputs 0.45 v i ol e 32 ma (note 1) control outputs 0.45 v i ol e 16 ma (note 2) v oh output high voltage command outputs 2.4 v i oh eb 5 ma (note 1) v cc b 0.5 v i oh eb 1 ma (note 1) control outputs 2.4 v i oh eb 1 ma (note 2) v cc b 0.5 v i oh eb 0.2 ma (note 2) i il input leakage current g 10 m a0v s v in s v cc i lo output leakage current g 10 m a 0.45v s v out s v cc i cc power supply current 75 ma i cc s power supply current (static) 3 ma (note 3) c clk clk input capacitance 12 pf f c e 1 mhz c i input capacitance 10 pf f c e 1 mhz c o input/outut capacitance 20 pf f c e 1 mhz notes: 1. commands outputs are inta , iorc , iowc , mrdc and mwrc . 2. control outputs are dt/r , den, ale and mce. 3. tested while outputs are unloaded, and inputs at v cc or v ss . 13
m82C288 a.c. characteristics (over specified operating conditions) ac timings are referenced to 0.8v and 2.0v points of signals as illustrated in data sheet waveforms, unless otherwise noted. symbol parameter 6 mhz 8 mhz 10 mhz unit comments (advance) (advance) (advance) -6 -6 -8 -8 -10 -10 min max min max min max 1 clk period 83 250 62 250 50 250 ns 2 clk high time 25 20 16 ns at 3.6v 3 clk low time 20 15 12 ns at 1.0v 4 clk rise time 10 10 8 ns 1.0v to 3.6v 5 clk fall time 10 10 8 ns 3.6v to 1.0v 6 m/io and status 28 22 18 ns setup time 7 m/io and status 1 1 1 ns hold time 8 cenl setup time 30 20 15 ns 9 cenl hold time 1 1 1 ns 10 ready setup time 50 38 26 ns 11 ready hold time 35 25 25 ns 12 cmdly setup time 25 20 15 ns 13 cmdly hold time 1 1 1 ns 14 aen setup time 25 20 15 ns (note 3) 15 aen hold time 0 0 0 ns (note 3) 16 ale, mce active 3 25 3 20 3 16 ns (note 4) delay from clk 17 ale, mce inactive 35 25 19 ns (note 4) delay from clk 18 den (write) 35 35 23 ns (note 4) inactive from cenl 19 dt/r low from clk 40 25 23 ns (note 4) 20 den (read) active 0 50 0 35 0 21 ns (note 4) from dt/r 21 den (read) inactive 5 40 5 35 5 21 ns (note 4) dly from clk 22 dt/r high from 3 45 3 35 3 20 ns (note 4) den inactive 23 den (write) active 35 30 23 ns (note 4) delay from clk 24 den (write) inactive 3 35 3 30 3 19 ns (note 4) dly from clk 14
m82C288 a.c. characteristics (over specified operating conditions) ac timings are referenced to 0.8v and 2.0v points of signals as illustrated in data sheet waveforms, unless otherwise noted. (continued) symbol parameter 6 mhz 8 mhz 10 mhz unit comments (advance) (advance) (advance) -6 -6 -8 -8 -10 -10 min max min max min max 25 den inactive from cen 40 30 25 ns (note 4) 26 den active from cen 35 30 24 ns (note 4) 27 dt/r high from clk 50 35 25 ns (note 4) (when cen e low) 28 den active from aen 35 30 26 ns (note 4) 29 cmd active delay from clk 3 40 3 25 3 21 ns (note 5) 30 cmd inactive delay from clk 5 30 5 25 5 20 ns (note 5) 31 cmd active from cen 45 25 25 ns (note 5) 32 cmd inactive from cen 25 25 25 ns (note 5) 33 cmd inactive enable from aen 40 40 40 ns (note 5) 34 cmd float delay from aen 40 40 40 ns (note 6) 35 mb setup time 25 20 15 ns 36 mb hold time 0 0 0 ns 37 command inactive enable 40 40 40 ns (note 5) from mb v 38 command float time from mb u 40 40 40 ns (note 6) 39 den inactive from mb u 40 30 26 ns (note 4) 40 den active from mb v 35 30 26 ns (note 4) notes: 3. aen is an asynchronous input. this specification is for testing purposes only, to assure recognition at a specific clk edge. 4. control output load: ci e 150 pf. 5. command output load: ci e 300 pf. 6. float condition occurs when output current is less than i lo in magnitude. 271077 13 note 7: ac drive and measurement pointseclk input 15
m82C288 271077 14 note 8: ac setup, hold and delay time measurementegeneral 271077 15 note 9: ac test loading on outputs waveforms clk characteristics 271077 16 16
m82C288 waveforms (continued) status, ale, mce, characteristics 271077 17 cenl, cmdly, den characteristics with mb e 0 and cen e 1 during write cycle 271077 18 read cycle characteristics with mb e 0 and cen e 1 271077 19 17
m82C288 waveforms (continued) write cycle characteristic with mb e 0 and cen e 1 271077 20 cen characteristics with mb e 0 271077 21 18
m82C288 waveforms (continued) aen characteristics with mb e 1 271077 22 note: 1. aen is an asynchronous input. aen setup and hold time is specified to guarantee the response shown in the waveforms. mb characteristics with aen /cen e high 271077 23 19
m82C288 waveforms (continued) mb characteristics with aen /cen e high (continued) 271077 24 271077 25 notes: 1. mb is an asynchronous input. mb setup and hold times specified to guarantee the response shown in the waveforms. 2. if the setup time, t35, is met two clock cycles will occur before cmd becomes active after the falling edge of mb. intel corporation, 2200 mission college blvd., santa clara, ca 95052; tel. (408) 765-8080 printed in u.s.a./xxxx/1296/b10m/xx xx

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